1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a structure of one-transistor.one-capacitor type dynamic memory cells.
2. Description of the Related Art
Various structures have been proposed as one-transistor.one-capacitor type dynamic memory cells for providing memory cell arrays so as to achieve high integration density. FIG. 5 shows an SPT cell as one such example. In an arrangement shown in FIG. 5, reference numeral 51 is a P.sup.+ -type semiconductor substrate to which a ground potential Vss is applied. 52 a P-type epitaxial layer grown on the substrate 51, 53 an N-type well region provided in a part of a region of the epitaxial layer 52 and biased to a positive electric potential, and 54 an isolation region, respectively. A cell capacitor is provided as an insulated gate type capacitor (MOS capacitor) which includes a thin insulating film 55, formed on an inner surface of a trench extending to the substrate 51 through both the well region 53 and the epitaxial layer 52, and a P.sup.+ -type polysilicon layer 56 for a charge storage electrode filled in the trench. In this case, the substrate 51 acts as a capacitor plate electrode.
A cell transistor for charge transfer is provided on the surface portion of the well region 53 and comprised of P.sup.+ -type source and drain regions 57 and 58 formed in the well region 53 and a gate electrode 60 disposed through a gate insulating film 59 above a channel region defined between the source and drain regions. The upper surface of the drain region 58 is connected through a conductive film 61 to the polysilicon layer 56 in the trench. The gate electrode 60 is formed of, for example, silicides and serves as a part of a word line for the memory cell array. 60a is a word line for an adjacent row, 62 an interlevel insulator, and 63 a bit line which is in contact with the source region 57, respectively.
However, the dynamic memory cell has associated therewith a problem as described in more detail in the document "Parasitic Leakage in DRAM Trench Storage Capacitor Vertical Gated Diodes, W. P. Noble et al. IEDM 1987 Tech Digest, PP 340 to 343". That is, as shown in FIG. 6, since the insulating film 55 on the inner surface of the trench acts as a gate insulating film and the P.sup.+ -type polysilicon layer 56 for the charge storage electrode acts as a control gate, a leakage current may flow through a junction between the N-type well region 53 and the P.sup.+ -type substrate 51. In this case, the dependence of the junction leakage current associated with a voltage between the P.sup.+ -type polysilicon layer 56 for the storage electrode and the P.sup.+ -type substrate 51 will be obtained as shown in FIG. 7 when the ambient temperature and thickness of the insulating film 55 on the trench are used as parameters. From this it will be apparent that the junction leakage current is increased with a decrease in the thickness of the insulating film 55 on the inner surface of the trench.
However, the insulating film 55 on the inner surface of the trench should have decreased thickness in order to provide good memory cells and to obtain higher storage capacitance. In this case however the junction leakage current will be increased, thereby increasing the power consumption of the dynamic memory device.
As described above, the conventional dynamic memory cell involves the problem such that, even if the insulating film provided on the inner surface of the capacitor formation trench has reduced thickness so as to increase the storage capacitance of the memory cell, the junction leakage current between the well region and the substrate will be increased, thereby increasing the power consumption of the dynamic memory device.